1. Field of the Invention
The present invention relates to a thin film transistor and a method of manufacturing thereof, and more particularly, to a thin film transistor of a polysilicon film and a method of manufacturing thereof.
2. Description of the Background Art
A thin film transistor (TFT) is a known semiconductor device, used as a load transistor of a highly integrated SRAM, and a drive transistor for a liquid crystal panel display. To meet the demand of high performance of devices employing TFTs, significant improvement in the electric characteristics of a TFT itself is desired.
A TFT is generally formed of a polysilicon film. The electric characteristics thereof are greatly affected by the grain boundary in a field region. The localized level depending on a grain boundary acts as a capture trap of carriers and as a generation center of an electron-hole pair. The presence of a grain boundary in a channel region of a TFT results in the capture of carriers to form a potential barrier by which passage of carriers are prevented. This induces a problem of lowering the ON current of a TFT. The presence of a grain boundary in the pn junction at the drain side will cause generation of a great amount of electron-hole pairs, resulting in increase of OFF current in a TFT. Conventionally, the electric characteristics of a TFT was improved by increasing the grain size of polysilicon for the channel to reduce the number of grain boundaries.
FIG. 80 is a sectional view of a conventional TFT for describing a method of manufacturing thereof; FIG. 81 is a plan view of the conventional TFT of FIG. 80; and FIG. 82 is a perspective view of a TFT formed according to a conventional manufacturing method.
A conventional manufacturing process of a TFT will be described hereinafter with reference to FIGS. 80-82.
Referring to FIG. 80, a polysilicon layer (not shown) of approximately 1500 .ANG. in thickness is formed by CVD on an insulating film 101, which is patterned to result in a gate electrode 102. A gate insulating film 103 of approximately 300 .ANG. in thickness is formed so as to cover gate electrode 102 by CVD. An amorphous silicon layer 104 is formed by CVD on gate insulating film 103 to a thickness of approximately 800 .ANG.. A heat treatment at a temperature condition of approximately 600.degree. C. is applied to solid phase grow an amorphous silicon layer 104. Thus, polysilicon 105 as shown in FIG. 81 is formed. Referring to FIG. 81, there is a grain boundary 106 at the boundary region of polysilicon 105. By growing polysilicon 105 according to the above-described process, polysilicon 105 having a grain size of approximately several thousand .ANG. can be formed. Since the grain size of polysilicon formed by CVD is approximately 100 .ANG., the above-described manufacturing process provides polysilicon 105 of a grain size several ten times thereof.
Then, source/drain regions 111 and 112, and a field 150 are formed.
FIG. 83 is a graph showing the electric characteristics of a TFT obtained by the conventional manufacturing method of FIG. 82. Referring to FIG. 83, gate voltage is plotted along the abscissa, and drain current is plotted along the ordinate. The drain current plotted along the ordinate shows the measured result of a pattern where 10000 TFTs are connected in parallel, each TFT having a channel length of 1.3 .mu.m and a channel width of 0.6 .mu.m. The TFT shown in FIG. 82 is a solid phase grown poly TFT. It is apparent from the graph of FIG. 82 that the ON current is one order of magnitude greater than that of a CVD poly TFT manufactured by CVD. Conventionally, the characteristics of a TFT was improved by forming polysilicon 105 increased in grain size by solid phase growing amorphous silicon layer 104, as shown in FIG. 82.
However, it is to be noted that the data shown in FIG. 83 represents the average value of 10000 TFTs. The property of each TFT for all the 10000 TFTs is not necessarily improved. FIG. 84 is a graph showing the electric characteristics of three single TFTs on the same wafer manufactured according to the process shown in FIGS. 80-82. It is appreciated from the graph of FIG. 84 that there is a variation of approximately one order of magnitude in the drain current between each of the three TFTs.
This variation is due to the fact that the crystals are grown in random since there is no selectivity in the solid phase growth when converting amorphous silicon layer 104 into polysilicon 105. A TFT with a grain boundary in the channel or a TFT with no grain boundary will be formed in random, resulting in difference in the characteristics of each TFT as shown in FIG. 84. Although it can be observed that the grain size of the solid phase grown polysilicon 105 according to the process shown in FIG. 81 is increased in average, the grain is not in uniform, and there are partially extremely small grains. The presence of such small grains in a channel portion of a TFT will degrade the characteristics of a TFT. This is also considered to be the cause of reducing the uniformity of characteristics of each TFT.
Thus, it was difficult to selectively grow polysilicon 105 according to the above-described method of forming polysilicon 105 having a large grain size from an amorphous silicon layer 104. This results in a problem that there is variation in the characteristics between each TFT.